Interview question for Physical design
1.What are the types in physical verification?
LVS (layout vs schematic).
DRC (design rule constrain check).
ERC (electric rule check).
LEC (logical equivalence check).
2.How to fix setup and hold violations at a time?
It is not possible to fix both at a time because if we increase the delay in data path it’s good for hold and bad for setup.But there is only one way to fix it.
• Buffer the data path for hold fix.
• Slow the clock frequency for setup fix (this is not a valid fix,but we don’t have other option).
3.How can you avoid cross-talk?
a) Increase the spacing between the aggressor and victim nets.
c) Maintain the stable supply.
d) Increase the drive strength of cell.
e) Layer jumping.
f) Victim net width increasing then resistance decreases.
g) Guard ring.
h) Cell sizing (up sizing).
4. How Do You Reduce Power Dissipation Using High Vt And Low Vt On Your Design?
1. Use HVT cells for timing paths having +ve slacks.
2. Use LVT cells for timing paths having -ve slacks.
HVT cells have a larger delay but less leakage. +ve slack in a design is not useful as having only some paths working faster will not help overall design. We are good if the slack is 0. In such cases give up the slack by using HVT cells but gain on power dissipation.
LVT cells are very fast but very leaky. Limit the use of LVT cells to only those paths that have difficulty in closing time.
5. What is cross-talk?
It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.When two nets are in parallel the electric field of one net is effects the other net which is nearer to it.This called cross-talk effect.
6. How Many Clocks You Had In Your Designs? How Did You Do Cts For The Same?
I had 5 clocks in my designs, sys_clk, sys_rclk, uart_clk, g_clk and scan_clk, where sys_clk, g_clk and uart_clk logically exclusive to scan_clk.
7. What Is The Importance Of Ir Drop Analysis?
IR drop determines the level of voltage at the pins of standard cells. Value of acceptable IR drop will be decided at the start of the project and it is one of the factors used to determine the derate value.
If the value of IR drop is more than the acceptable value, it calls to change the derate value. Without this change, timing calculation becomes optimistic. For example setup slack calculated by the tool is less than the reality.
8. Do You Know About Input Vector Controlled Method Of Leakage Reduction?
Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction.
9. How Can You Reduce Dynamic Power?
o Reduce switching activity by designing good RTL
o Clock gating
o Architectural improvements
o Reduce supply voltage
o Use multiple voltage domains-Multi vdd
10. what are the other solution other than increasing power line width and providing more number of straps to IR drop?
Below are some of the solution to IR drop problem
Spreading the macros
Spreading standard cells
Usage of suitable blockage
11.Which is suitable place to insert buffer, in order to fix setup violation in reg to reg path? Is it near to launch or setup flop, Justify your answer?
Buffer insertion is one of the method to overcome setup violation, Other methods are sizing of cells, Minimizing the data path etc. Lets assume that only insertion of buffer will solve the problem, then insert them Near to capture flop, Because there could be a chance other paths may be passing or originating from the launch flop. In that case buffer insertion may could hamper others paths of launch flipflop. there is a chance it will improve all those paths or degrade. If all paths have violation in launch flop also, then we can insert buffer near to launch flop. It could improve slack.
12. What are the challenges in the project?
Above answer you need to give according to your project common challenges could be power planning- because of lots of IR drop issue
1. Could be power target-because more dynamic and leakage power
2. It could be floorplanning issues in placing macro.
3. It could be CTS and CTO, because there may be chance you have to handle lots of clocks and clock domain crossing (CDC)
4. you might be facing challenges in timing fixtures
5. you might be facing library preparation, you may need to find some inconsistency in libraries.
13. What is scan chain reordering?
It is the process of re connecting the scan chains in the design to optimize for routing by reordering the scan chain connection which improves timing and congestion.
14. What is lookup table?
The table is drawn by using input transition and output load values.It is used to calculate the cell delay.
15. What does we do for low power design?
We apply low power techniques
• Clock gating.
• Multi voltage design.
• Power gating.
• Multiple vt libraries.
16. What are the types of checks done in prime time?
a) Timing (setup,hold,transition).
b) Design constraints.
e) Clock skew.
17. What analysis we do during floor plan?
a) Overlapping of macros.
b) Allowable IR drop.
c) Global route congestion.
d) Physical information of the design.
18. What are the different types of delay models?
a) WLM (wire load model)
b) NLDM ( non linear delay model)
c) CCS (composite current source)