Interview questions for Physical design engineers

Physical design engineers specialize in the development and construction of circuit layouts for microchips, processors, and other electronic architectures. They prepare circuit design plans, develop and test prototypes, and optimize circuit output.

When interviewing physical design engineers, look for candidates who exhibit advanced circuit design knowledge and the ability to evaluate the performance of semiconductor devices and components.

1. Can you describe your approach to preparing physical design projects?

Highlights the candidate’s experience in planning the stages of physical design projects and whether they demonstrate a collaborative approach.

2. Which methods to reduce circuit delays are often overlooked?

Reveals the candidate’s practical knowledge and experience, as well as their ability to optimize circuit performance.

3. What are the types in physical verification?

LVS (layout vs schematic).
DRC (design rule constrain check).
ERC (electric rule check).
LEC (logical equivalence check).

4. Which steps do you follow in testing design prototypes?

Assesses the candidate’s knowledge of prototype testing procedures, and their ability to proactively prevent design faults.

5. How to fix setup and hold violations at a time?

It is not possible to fix both at a time because if we increase the delay in data path it’s good for hold and bad for setup.But there is only one way to fix it.
• Buffer the data path for hold fix.
• Slow the clock frequency for setup fix (this is not a valid fix,but we don’t have other option).

6. How can you avoid cross-talk?

a) Increase the spacing between the aggressor and victim nets.
b) Shielding.
c) Maintain the stable supply.
d) Increase the drive strength of cell.
e) Layer jumping.
f) Victim net width increasing then resistance decreases.
g) Guard ring.
h) Cell sizing (up sizing).

7. Can you tell me about a major success you had as a physical design engineer?

Evaluates the candidate’s knowledge and experience in physical design engineering, as well as their ability to design complex circuits.

8. What is cross-talk?

It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.When two nets are in parallel the electric field of one net is effects the other net which is nearer to it.This called cross-talk effect.

9. What is scan chain reordering?

It is the process of re connecting the scan chains in the design to optimize for routing by reordering the scan chain connection which improves timing and congestion.

10. How do you calculate the resistances and capacitances of a design?

Tests the candidate’s knowledge of RC extraction fundamentals, and their ability to calculate bandwidth, quality factors, and corner points.
Did You Get Antenna Problem In Your Project For All The Metal Layers?

11. How Did You Fix Them?

Metal Jumper and Antenna diode are two methods to resolve Antenna violations. But Metal Jumper is preferred approach as it does not need change to the Netlist and placement. This methodology works for antenna violations on all metal layers except for the top most layer. In this methodology, we will switch the small portion of routing to higher level metal close to the location of failing gate. This will make sure that accumulated charges on metal layer does not affect the gate as gate will not be connected to the charge carrying metal route until higher level metal is manufactured.
For example, lets say antenna violation is in M2. This means that M2 has enough area to accumulate large charge that induces high electron voltage to destroy the gate. To solve this problem, we cut a portion of M2 close to failing gate and move the routing to M3. This makes sure that when M2 is being manufactured, it does not get connected to gate. Connection happens only when M3 gets manufactured which is much later in time. By then charges on Metal M2 would have leaked away.

12. What is the concept of rows in the floor plan?

The std-cells in the design are placed in rows.All rows have equal height and spacing.The width of the row can vary.The std-cell in the row get the power and ground connection from vdd and vss rails.Sometimes technology allows the rows to be flip.So they can share the power and ground rails in vdd-vss-vdd patron.

13. How Do You Reduce Power Dissipation Using High Vt And Low Vt On Your Design?

1. Use HVT cells for timing paths having +ve slacks.
2. Use LVT cells for timing paths having -ve slacks.
HVT cells have a larger delay but less leakage. +ve slack in a design is not useful as having only some paths working faster will not help overall design. We are good if the slack is 0. In such cases give up the slack by using HVT cells but gain on power dissipation.
LVT cells are very fast but very leaky. Limit the use of LVT cells to only those paths that have difficulty in closing time.

14. What Are The Various Statistics Available In Ir Drop Reports?

1. IR drop info for VDD/ VSS.
2. Maximum current through VDD/VSS.
3. Number of current sources for VDD/VSS.
4. Utilization of metal layers used.
5. EM information for signal and via.

15. In A Reg To Reg Path If You Have Setup Problem Where Will You Insert Buffer-near To Launching Flop Or Capture Flop? Why?

o (buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must insert buffer !)
o Near to capture path.
o Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degarde. If all those paths have voilation then you may insert buffer nearer to launch flop provided it improves slack.

16. What are the advantages of NDR’s?

a) By applying the double width we can avoid the EM.
b) By applying double spacing we can avoid the cross-talk.
c) Help’s to avoid congestion at lower metal layer.
d) Help’s pin accessibility of std-cells .