Job Information
Job Description
JOB description:
• Own execution and deliver Timing signoff for Large subsystem / full chip STA
• Develop timing methodologies to streamline execution and solve critical timing problems
• Debug timing constraint issues, make edits to fix them
• Achieving QOR goals , Debug timing QOR issues in primetime
• Timing, Noise ECO creation using PT ECO, Tweaker
• Executing floorplan based Large hierarchical designs / full chip synthesis of designs
• • Low Power cleanup/debug/fixes/suggestions
Job requirements :
• Should be hands on expereince in full chip STA
• Should be hands on STA Flow experience
• Should be hands on expereince in full chip synthesis , hierarchical synthesis
• Should be hands on low power synthesis
• Good flow understanding, scripting and Debug
• Must have knowledge on RTL reading, Synthesis optimization, SDC, clocking, low power (UPF) and DFT
• Should be hands on COnformal and Formality flow experience from RTL to Netlist
• Must have LEC debugging skills – aborts, mapping rules, optimization options, UPF debug
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